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介绍了一种基于数字信号处理器(DSP)和现场可编程门阵列(FPGA)的低频时码接收机的硬件组成,描述了该接收机系统实现时间同步的方法,阐述了DSP和FP-GA的软件设计,给出了测试和仿真结果。该设计方案具有精度高、可靠性强、扩展性好等优点。
Abstract：The hardware of a low frequency time-code receiver which was designed with FPGA(field programmable gate array)and DSP(digital signal processor)is introduced.The method of realizing the time synchronization for the receiver system is described.The software developed for DSP and FPGA is expounded,and the results of test and simulation are presented.The design is characterized by high accuracy,good reliability,fair extensibility,etc.
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基本信息:
中图分类号:P127.1
引用信息:
[1]李国栋,许林生.一种基于DSP和FPGA的低频时码接收机设计[J].时间频率学报,2006(01):27-34.
2006-06-30
2006-06-30